RING COUNTER

A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last flip flop connected to the input of the first. It is initialized such that only one of the flip flop output is 1 while the remainder is 0. The 1 bit is circulated so the state repeats every n clock cycles if n flip-flops are used. The "MOD" or "MODULUS" of a counter is the number of unique states. The MOD of the n flip flop ring counter is n.
It can be implemented using D-type flip-flops (or JK-type flip-flops). And this below, using the D Flip-flops

  
  • Enable the flips flops by clicking on the RESET (Green) switch. The RESET switch is a on/off switch (similar to a room light switch)
  • Click on CLK (Purple) switch and observe the changes in the outputs of the flip flops. The CLK switch is a momentary switch (similar to a door bell switch - normally off).
  • The D flip flop clock has a rising edge CLK input. For example Q1 behaves as follows:
    • The D input value just before the CLK rising edge is noted (Q0).
    • When CLK rising edge occurs, Q1 is assigned the previously noted D value (Q0)
  • And this is the TIMING DIAGRAM






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